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1/22 tda7429 june 2004 1features 3 stereo inputs input attenuation control in 0.5db step treble middle and bass control three surround modes are available ? music: 4 selectable responses ? movie and simulated: 256 selectable responses four speakers attenuators: ? 4 independent speakers control in 1db steps for balance facility ? independent mute function all functions programmable via serial bus 2 description the tda7429 is volume tone (bass middle and tre- ble) balance ( left/right) processo rs for quality audio applications in tv and hi-fi systems. it reproduces surround sound by using programma- ble phase shifters and a signal matrix. control of all the functions is accomplished by serial bus. the ac signal setting is obtained by resistor net- works and switches combined with operational ampli- fiers. thanks to the used bipolar/cmos technology, low distortion, low noise and dc stepping are obtained. digitally controlled audio processor with surround sound matrix figure 2. pin connection (tqfp44) 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 var_l rearin rearout hp1 lp1 hp2. bass_li bass_lo basso_r basso_l var_r bass_ro bass_ri middle_lo middle_li middle_ri middle_ro treble_r treble_l agnd sda scl lp ps1 ps2 ps3 v s ps4 cref r_in4 r_in3 r_in2 r_in1 l_in4 auxout_l auxout_r r_out dig_gnd l_out monitor_l monitor_r l_in1 l_in3 l_in2 d96au532 12 13 14 15 16 rev. 6 figure 1. package t able 1. order codes part number package tda7429s sdip42 tda7429t tqfp44 TDA7429T13TR tape & reel sdip42 tqfp44
tda7429 2/22 figure 3. pin connection (sdip42) table 2. absolute maximum ratings table 3. quick reference data table 4. thermal data symbol parameter value unit v s operating supply voltage 11 v t amb operating ambient temperature 0 to 70 c t stg storage temperature range -55 to 150 c symbol parameter min. typ. max. unit v s supply voltage 7 9 10.2 v v cl max input signal handling 2 v rms thd total harmonic distortion v = 0.1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio v out = 1vrms (mode = off) 106 db s c channel separation f = 1khz 90 db treble control (2db step) -14 14 db middle control (2db step) -14 14 db bass control (2db step) -14 14 db balance control 1db step (lch, rch) -79 0 db mute attenuation 100 db symbol parameter value unit r th j-pin thermal resistance junction-pins 85 c/w 1 3 2 4 5 6 7 8 9 auxout_r auxout_l l_in3 l_in1 l_in2 monitor_l monitor_r r_in1 r_in2 37 36 35 34 33 31 32 30 29 d97au623 10 11 12 13 14 42 41 40 39 38 r_in3 cref v s 15 16 middle_ri treble_r treble_l scl sda dig_gnd r_out 28 27 26 24 25 23 22 17 18 19 20 21 lp1 hp1 hp2 rearout rearin basso_l var_l var_r basso_r ps4 ps3 ps2 ps1 lp bass_lo bass_li bass_ro middle_lo bass_ri middle_li middle_ro l_out agnd
3/22 tda7429 figure 4. test circuit (tda7429s) figure 5. test circuit (tda7429t) ps4 22nf ps3 22nf ps2 4.7nf ps1 100nf lp 1.2nf lp1 5.6nf hp1 680nf var_l 2.2 f hp2 basso_l var_r basso_r auxout_l auxout_r l_out r_out v s cref 100nf 10 f 22 f 220nf r_in3 0.47 f r_in2 0.47 f dig_gnd scl sda agnd 18nf 2.7k middle_lo middle_li 22nf 18nf 2.7k middle_ro middle_ri 22nf 100nf 5.6k bass_lo bass_li 100nf 100nf 5.6k bass_ro bass_ri 100nf treble_l 5.6nf d97au626 2.2 f treble_r 5.6nf monitor_r 100nf 42 1 14 2 3 4 5 6 23 24 37 19 20 21 22 41 15 16 17 18 32 31 30 29 28 27 26 25 13 12 11 87 40 39 rearin 2.2 f rearout 910 r_in1 0.47 f 38 l_in1 0.47 f 35 l_in2 0.47 f 34 l_in3 0.47 f 33 monitor_l 36 ps4 22nf ps3 22nf ps2 4.7nf ps1 100nf lp 1.2nf lp1 5.6nf hp1 680nf var-l 2.2 f hp2 basso-l var-r basso-r auxout-l auxout-r l-out r-out v s cref 100n f 10 f 22 f 220nf r-in4 0.47 f r-in3 0.47 f r-in2 0.47 f dig-gnd scl sda agnd 18nf 2 .7k middle-lo middle-li 22nf 18nf 2 .7k middle-ro middle-ri 22nf 100nf 5.6k bass-lo bass-li 100nf 100nf 5.6k bass-ro bass-ri 100nf treble-l 5.6nf d96au533 2.2 f treble-r 5.6nf monitor_r 100nf 39 40 9 41 42 43 44 1 18 19 33 14 15 16 17 38 10 11 12 13 27 26 25 24 23 22 21 20 876 32 37 36 35 rearin 2.2 f rearout 45 r-in1 0.47 f 34 l-in1 0.47 f 31 l-in2 0.47 f 30 l-in3 0.47 f 29 l-in4 0.47 f 28 monitor_l 32
tda7429 4/22 figure 6. block diagram (tda7429t) l-in1 rlp1 l-r 0.47 f supply v s agnd cref treble 18nf middle 2.7k middle-li middle-lo 22nf rm bass bass-li mute d96au513 mute i 2 c bus decoder + latches spkr att rec att treble middle bass 18nf 22nf 2.7k 5.6nf mute spkr att mute rec att scl sda dig gnd r-out auxout-r l-out auxout-l 22 f + - + - + rhp1 lp1 hp1 hp2 5.6nf 680nf - + r6 r5 r-in4 0.47 f 50k ps1 90hz 100nf ps1 rps1 sim movie/ music music off ps2 4khz ps3 400hz ps4 400hz 4.7nf ps2 rps2 22nf ps3 rps3 22nf ps4 rps4 movie/sim mixing amp lpf 9khz effect control mixing amp 1.2nf lp middle-ri middle-ro 31 1 2 3 43 42 41 40 37 39 20 38 44 15 14 11 25 17 16 13 27 22 21 23 24 26 monitor r treble-r 79db control 5.6nf treble-l 100nf 5.6k 100nf bass-lo 100nf 100nf 5.6k bass-ri bass-ro 79db control 79db control 2.2 f basso-r var-r 30k + - + - 2.2 f basso-l var-l 30k 79db control 10 7 6 8 9 12 18 33 19 50k 0.47 f 50k 0.47 f 50k 0.47 f 50k 0.47 f 50k 0.47 f 50k 0.47 f 50k 31.5db control r-in3 r-in2 r-in1 31.5db control l-in2 l-in3 l-in4 2.2 f 50k rearin rearout 30 29 28 34 35 36 45 vref off surr off surr rm rb surr rear fix 3band surr rear fix 3band fix var rb fix var the switches position matches the reset condition 32 monitor l
5/22 tda7429 figure 7. block diagram (tda7429s) l_in1 rlp1 l-r 0.47 f supply v s agnd cref treble 18nf middle 2.7k middle_li middle_lo 22nf rm bass bass_li mute d97au624a mute i 2 c bus decoder + latches spkr att rec att treble middle bass 18nf 22nf 2.7k 5.6nf mute spkr att mute rec att scl sda dig gnd r_out auxout_r l_out auxout_l 22 f + - + - + rhp1 lp1 hp1 hp2 5.6nf 680nf - + r6 r5 r_in3 0.47 f 50k ps1 90hz 100nf ps1 rps1 sim movie/ music music off ps2 4khz ps3 400hz ps4 400hz 4.7nf ps2 rps2 22nf ps3 rps3 22nf ps4 rps4 movie/sim mixing amp lpf 9khz effect control mixing amp 1.2nf lp middle_ri middle_ro 35 6 7 8 43 21 40 42 25 41 5 20 19 16 30 22 21 18 32 27 26 28 29 31 monitor_r treble_r 79db control 5.6nf treble_l 100nf 5.6k 100nf bass_lo 100nf 100nf 5.6k bass_ri bass_ro 79db control 79db control 2.2 f basso_r var_r 30k + - + - 2.2 f basso_l var_l 30k 79db control 15 12 11 13 14 17 23 37 24 50k 0.47 f 50k 0.47 f 50k 0.47 f 50k 0.47 f 50k 31.5db control r_in2 r_in1 31.5db control l_in2 l_in3 2.2 f 50k rearin rearout 34 33 38 39 910 vref off surr off surr rm rb surr rear fix 3band surr rear fix 3band fix var rb fix var the switches position matches the reset condition 36 monitor_l
tda7429 6/22 table 5. electrical characteristcs (refer to the test circuit t amb = 25c, v s = 9v, r l = 10k ? , v in = 1vrms; r g = 600 ? , all controls flat (g = 0db), l+r ctrl = +4db, mode = off; f = 1khz unless otherwise specified). symbol parameter test condition min. typ. max. unit supply v s supply voltage 7 9 10.2 v i s supply current 10 18 26 ma svr ripple rejection l ch / r ch out , mode = off 60 80 db input stage r in input resistance 35 50 65 k ? v cl clipping level thd = 0.3% 2 2.5 v rms c range control range 31.5 db a vmin min. attenuation -1 0 1 db a vmax max. attenuation 31 31.5 32 db a step step resolution 0.5 1 db bass control g b control range max. boost/cut 11.5 14.0 16.0 db b step step resolution 1 2 3 db r b internal feedback resistance 32 44 56 k ? middle control g m control range max. boost/cut 11.5 14.0 16.0 db m step step resolution 1 2 3 db r m internal feedback resistance 17.5 25 32.5 k ? treble control g t control range max. boost/cut 13.0 14.0 15.0 db t step step resolution 1 2 3 db effect control c range control range -21 -6 db s step step resolution 0.5 1 1.5 db surroubnd soubnd matrix phase r ps10 phase shifter 1: d1 = 0, d0 = 0 8.3 11.8 15.2 k ? r ps11 phase shifter 1: d1 = 0, d0 = 1 10 14.1 18.3 k ? r ps12 phase shifter 1: d1 = 1, d0 = 0 12.6 17.9 23.3 k ? r ps13 phase shifter 1: d1 = 1, d0 = 1 26.4 37.3 48.85 k ? r ps20 phase shifter 2: d3 = 0, d2 = 0 4 5.6 7.2 k ?
7/22 tda7429 surround sound matrix test condition (phase resistor selection d0=0, d1=1, d2=0. d3=1, d4=0, d5=1, d6=0, d7=1 r ps21 phase shifter 2: d3 = 0, d2 = 1 4.8 6.8 8.7 k ? r ps22 phase shifter 2: d3 = 1, d2 = 0 6 8.4 10.9 k ? r ps23 phase shifter 2: d3 = 1, d2 = 1 12.9 18.3 23.7 k ? r ps30 phase shifter 3: d5 = 0, d4 = 0 8.5 12.1 15.6 k ? r ps31 phase shifter 3: d5 = 0, d4 = 1 10.2 14.5 18.7 k ? r ps32 phase shifter 3: d5 = 1, d4 = 0 12.7 18.1 23.3 k ? r ps33 phase shifter 3: d5 = 1, d4 = 1 27.4 39.1 50.75 k ? r ps40 phase shifter 4: d7 = 0, d6 = 0 8.5 12.1 15.6 k ? r ps41 phase shifter 4: d7 = 0, d6 = 1 10.2 14.5 18.7 k ? r ps42 phase shifter 4: d7 = 1, d6 = 0 12.7 18.1 23.3 k ? r ps43 phase shifter 4: d7 = 1, d6 = 1 27.4 39.1 50.75 k ? g off in-phase gain (off) mode off, input signal of 1khz, 1.4 v p-p , r in r out , l in l out -1 0 1 db d goff lr in-phase gain difference (off) mode off, input signal of 1khz, 1.4 v p-p , r in r out , l in l out -1 0 1 db g mov in-phase gain (movie) movie mode, effect ctrl = -6db 1khz, 1.4 v p-p , r in r out , l in l out 8db d gmov lr in-phase gain difference (movie) movie mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p (r in r out ) - (l in l out ) 0db g mus in-phase gain (music) music mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p (r in r out ) , (l in l out ) 7db d gmus lr in-phase gain difference (music) music mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p (r in r out ) , (l in l out ) 0db l mon1 simulated l output 1 simulated mode, effect ctrl = -6db input signal of 250hz, 1.4 v p-p , r in and l in l out 4.5 db l mon2 simulated l output 2 simulated mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p , r in and l in l out ?4.0 db l mon3 simulated l output 3 simulated mode, effect ctrl = -6db input signal of 3.6khz, 1.4 v p-p , r in and l in l out 7.0 db r mon1 simulated r output 1 simulated mode, effect ctrl = -6db input signal of 250hz, 1.4 v p-p , r in and l in r out ? 4.5 db symbol parameter test condition min. typ. max. unit
tda7429 8/22 r mon2 simulated r output 2 simulated mode, effect ctrl = -6db input signal of 1khz, 1.4 v p-p , r in and l in r out 3.8 db r mon3 simulated r output 3 simulated mode, effect ctrl = -6db input signal of 3.6khz, 1.4 v p-p , r in and l in r out ? 20 db r lp1 low pass filter resistance 7 10 13 k ? r hpi high pass filter resistance 42 60 78 k ? r lpf lp pin impedance 7 10 13 k ? speaker & aux attenuators c range control range 79 db s step step resolution -0.5 1 1.5 db e a attenuation set error a v = 0 to -20db -1.5 0 1.5 db a v = -20 to -79db -3 0 2 db v dc dc steps adjacent att. steps -3 0 3 mv a mute output mute condition +70 100 db r vea input impedance 21 30 39 k ? audio outputs n o(off) output noise (off) output mute, flat bw = 20hz to 20khz 4 5 v rms v rms n o(mov) output noise (movie) mode = movie bw = 20hz to 20khz 30 v rms n o(mus) output noise (music) mode = music bw = 20hz to 20khz 30 v rms n o(mon) output noise (simulated) mode simulated bw = 20hz to 20khz 30 v rms d distorsion a v = 0 ; v in = 1v rms 0.01 0.1 % s c channel separation 70 90 db v ocl clipping level d = 0.3% 2 2.5 vrms r out output resistance 25 50 85 ? v out dc voltage level 3.8 v monitor outputs d distorsion a v = 0 ; v in = 1v rms 0.01 0.1 % s c channel separation 70 90 db v ocl clipping level d = 0.3% 2 2.5 vrms r out output resistance 20 50 85 ? v out dc voltage level 4.5 v symbol parameter test condition min. typ. max. unit
9/22 tda7429 3i 2 c bus interface data transmission from microprocessor to the tda7429 and viceversa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connect- ed). 3.1 data validity as shown in fig. 8, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 3.2 start and stop conditions as shown in fig.9 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. 3.3 byte format every byte transferred on the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. 3.4 acknowledge the master (mp) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 10). the peripheral (audioprocessor) that acknowledges has to pull-down (low) the sda line during this clock pulse. the audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. 3.5 transmission without acknowledge avoiding to detect the acknowledge of the audioprocessor, the p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking. bus inputs v il input low voltage 1v v ih input high voltage 3 v i in input current -5 +5 ma v o output voltage sda acknowledge i o = 1.6ma 0.4 v symbol parameter test condition min. typ. max. unit
tda7429 10/22 figure 8. data validity on the i 2 c bus figure 9. timing diagram of i 2 c bus figure 10. acknowledge on the i 2 c bus 4 software specification 4.1 interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the tda7429 address a subaddress bytes a sequence of data (n byte + achnowledge) a stop condition (p) figure 11. s da s cl data line stable, data valid change data allowed d99au1031 s cl s da start i 2 cbu s stop d99au1032 s cl 1 msb 23789 s da start acknowledgmen t from receiver d99au1033 s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au226a b data subaddress data 1 to data n
11/22 tda7429 5 examples 5.1 no incremental bus the tda7429 receives a start condition, the correct chip address, a subaddress with the msb = 0 (no incre- mental bus), n-datas (all these datas concern the subaddress selected), a stop condition. figure 12. 5.2 incremental bus the tda7429 receives a start condition, the correct chip address, a subaddress with the msb = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas subaddress from "1xxx1010" to "1xxx1111" of data are ignored.the data 1 concern thesubaddress sent, and the data 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition. figure 13. 6 data bytes address = 80(hex) 6.1 function selection table 6. the first byte (subaddress) b = 1 incremental bus; active b = 0 no incremental bus; x = indifferent 0,1 msb lsb subaddress d7 d6 d5 d4 d3 d2 d1 d0 b x x x 0 0 0 0 input attenuation b x x x 0 0 0 1 surround & out & effect control b x x x 0 0 1 0 phase resistor b x x x 0 0 1 1 bass & natural base bxxx0 1 0 0middle & treble b x x x 0 1 0 1 speaker attenuation "l" b x x x 0 1 1 0 speaker attenuation "r" bxxx0 1 1 1aux attenuation "l" bxxx1 0 0 0aux attenuation"r" b x x x 1 0 0 1 input multiplexer, & aux out s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au306 0 d3 subaddress data x x x d2 d1 d0 s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d95au307 1 d3 subaddress data 1 to data n x x x d2 d1 d0
tda7429 12/22 table 7. input attenuation selection input attenuation = 0 ~ -31.5db table 8. msb lsb input attenuation d7 d6 d5 d4 d3 d2 d1 d0 0.5 db steps x0000 x001-0.5 x010-1 x011-1.5 x100-2 x101-2.5 x110-3 x111-3.5 4 db steps x000 0 x001 -4 x010 -8 x011 -12 x100 -16 x101 -20 x110 -24 x111 -28 d7 d6 d5 d4 d3 d2 d1 d0 rear switch x 0 rearin, rearout pin active x 1 no rearin, rearout pin
13/22 tda7429 table 9. surround selection table 10. phase resistor selection msb lsb d7 d6 d5 d4 d3 d2 d1 d0 surround mode x00simulated x01music x10off x 1 1 movie out x0var x1fix effect control x0000 -6 x0001 -7 x0010 -8 x0011 -9 x0100 -10 x0101 -11 x0110 -12 x0111 -13 x1000 -14 x1001 -15 x1010 -16 x1011 -17 x1100 -18 x1101 -19 x1110 -20 x1111 -21 msb lsb surround phase resistor d7 d6 d5 d4 d3 d2 d1 d0 phase shift 1 (k ? ) 00 12 01 14 10 18 11 37 phase shift 2 (k ? ) 00 6 01 7 10 8 11 18 phase shift 3 (k ? ) 00 12 01 14 10 18 11 39 phase shift 4 (k ? ) 00 12 01 14 10 18 11 39
tda7429 14/22 table 11. bass selection table 12. speaker/aux att. r & l selection x = indifferent 0,1 speaker/aux attenuation = 0db ~ -79db msb lsb bass d7 d6 d5 d4 d3 d2 d1 d0 2 db steps xxx10000 -14 xxx10001 -12 xxx10010 -10 xxx10011 -8 xxx10100 -6 xxx10101 -4 xxx10110 -2 xxx10111 0 xxx11111 0 xxx11110 2 xxx11101 4 xxx11100 6 xxx11011 8 xxx11010 10 xxx11001 12 xxx11000 14 msb lsb speaker/aux att d7 d6 d5 d4 d3 d2 d1 d0 1 db steps x0000 x001-1 x010-2 x011-3 x100-4 x101-5 x110-6 x111-7 8 db steps x0000 0 x0001 -8 x0010 -16 x0011 -24 x0100 -32 x0101 -40 x0110 -48 x0111 -56 x1000 -64 x1001 -72 mute x101x x11xx
15/22 tda7429 table 13. middle & treble selection msb lsb middle d7 d6 d5 d4 d3 d2 d1 d0 2 db steps 0000 -14 0001 -12 0010 -10 0011 -8 0100 -6 0101 -4 0110 -2 0111 0 1111 0 1110 2 1101 4 1100 6 1011 8 1010 10 1001 12 1000 14 treble 2 db steps 0000 -14 0001 -12 0010 -10 0011 -8 0100 -6 0101 -4 0110 -2 0111 0 1111 0 1110 2 1101 4 1100 6 1011 8 1010 10 1001 12 1000 14
tda7429 16/22 table 14. input/recout l & r selection table 15. msb lsb d7 d6 d5 d4 d3 d2 d1 d0 input multiplexer x000in2 x010in3 x100in4 x110in1 aux out "l" x 0 0 0 ver 1 (3band) x 0 1 0 ver 2 (surr) x 1 0 0 ver 3 (rear) x110fix aux out "r" x 0 0 0 ver 1 (3band) x 0 1 0 ver 2 (surr) x 1 0 0 ver 3 (rear) x11 0 fix power on reset bass & middle 2db treble 0db surround & out control+ effect control off + fix + max attenuation speaker/aux attenuation l &r mute input attenuation + rear switch max attenuation + on natural base off input in1 figure 14. pin: vout ref figure 15. pin: treble-l, treble-r 25k v s d95au309 20 a gnd 10k v s d95au233a 20 a gnd gnd
17/22 tda7429 figure 16. pin: hp1 figure 17. pin: hp2 figure 18. pin: var-l, var-r, figure 19. pin: l-in, r-in, l-in2, r-in2, l-in3, r-in3, l-in4, r-in4, figure 20. pin: lp1 figure 21. pin: cref 10k 60k gnd v s lp1 hp2 d94au198 5.5k 60k gnd v s hp1 d94au199 20 a 5.5k 20 a v s 30k vref d95au227 sw gnd 50k gnd v s v ref d94au200 20 a 10k v s d94au211 20 a hp1 gnd 20k v s d95au336 20 a 20k gnd 42k
tda7429 18/22 figure 22. pin: scl, sda figure 23. pin: ps1, ps2, ps3, ps4, lp figure 24. pin: rearin figure 25. pin: l-out, r-out, monitor-l, monitor-r rearout, basso-l, basso-r, auxout_l, auxout_r figure 26. pin: bass-li, bass-ri, middle-li, middle-ri, figure 27. pin: bass-lo, bass-ro, middle- lo, middle-ro, d94au205 20 a gnd v s d95au308 20 a gnd 20 a v s 50k vref d95au229 sw gnd v s d95au230 20 a gnd 45k or 25k v s d95au231a 20 a bass-ro,middle-lo,middle-ro bass-lo gnd : bass : middle (*) v s d95au232 20 a bass-li,bass-ri,middle-li,middle-ri gnd (*) 45k : bass 25k : middle
19/22 tda7429 figure 28. tqfp44 (10 x 10) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 8.00 0.315 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 8.00 0.315 e 0.80 0.031 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?(min.), 3.5?(typ.), 7?(max.) tqfp44 (10 x 10 x 1.4mm) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 0076922 d
tda7429 20/22 figure 29. sdip42 mechanical data & package dimensions sdip42 (0.600") a1 b e b1 d 22 21 42 1 la e1 a2 c e1 e e2 gage plane .015 0,38 e2 e3 e sdip42 dim. mm inch min. typ. max. min. typ. max. a 5.08 0.20 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.38 0.46 0.56 0.0149 0.0181 0.0220 b1 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.60 0.629 e1 12.70 13.72 14.48 0.50 0.540 0.570 e 1.778 0.070 e1 15.24 0.60 e2 18.54 0.730 e3 1.52 0.060 l 2.54 3.30 3.56 0.10 0.130 0.140 outline and mechanical data
21/22 tda7429 table 16. revision history date revision description of changes january 2004 5 first issue in edocs dms june 2004 6 changed the style-sheet in compliance to the new ?corporate technical pubblications design guide?
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